Power Minimization in Heterogeneous Processing

Optimizing power during the partitioning and scheduling of tasks onto multiple heterogeneous VLSI processors is an important new problem. This paper presents a new methodology and initial analysis of power in heterogeneous systems for realtime compute intensive applications. Minimization of latency and interprocessor communication are studied, along with voltage scaling techniques to study relative power savings. Task duplication, data regeneration, loop winding and loop unrolling are also supported. A large complex real Industrial application, audio compression, donated by Motorola, is used to study the power savings using different heterogeneous system implementations. Results show that up to 10 times improvement in estimated power are attainable for this complex application. Data regeneration, task duplication, and loop unrolling techniques provided up to 51%, 6% and 20% savings in power respectively. This research is important for Industry since power dissipation consideration at the early stages of design is crucial for mapping high pe$ormance applications into costefficient and reliable heterogeneous systems.